Semiconductor VC Series①: Converging on AI Bottlenecks
Where are Tier-1 VCs placing bets in the expanding $975B semiconductor market? Strategies of Sequoia, a16z, Kleiner Perkins, Bessemer, and SoftBank compared through the lens of a CVC with semiconductor-process background. Part 1 of 3.
Where are Tier-1 VCs placing bets in the expanding $975B semiconductor market? Strategies of Sequoia, a16z, Kleiner Perkins, Bessemer, and SoftBank compared through the lens of a CVC with semiconductor-process background. Part 1 of 3.
Semiconductor VC Series ①: Converging on AI Bottlenecks
I came up through semiconductor process development. Semiconductors aren't an abstract investment category for me — they're an operational reality I've worked with.
When I moved to corporate VC and watched how Tier-1 VCs allocated capital, the pattern that jumped out was that they aren't buying chips — they're buying AI's constraints. This is Part 1 of a three-part series on what that thesis looks like across Sequoia, a16z, Kleiner Perkins, Bessemer, and SoftBank.
What's Actually Happening Behind the Boom
Let me put the picture down flat first.
In 2025 the global semiconductor market hit an all-time high of $791.7B (WSTS), with consensus pointing to $975B in 2026 as AI infrastructure pulls the whole stack. SEMI projects 300mm fab equipment spending of $133B in 2026 and $151B in 2027.
Read the surface and it looks like a chip boom. Read the VC books and it's something different: the bottlenecks — design throughput, data movement, packaging, and new computing paradigms — are where Tier-1 capital is concentrated.
Executive Summary
- AI infrastructure is the growth driver. The rise in market size and equipment investment signals sustained capital intensity, not easing supply constraints. For startups, securing production and testing capability is increasingly the key evaluation criterion.
- VC differentiation is in stage selection and partnership structure. Mega-seed architectural bets (a16z), design productivity (Sequoia/Bessemer), or M&A-driven vertical integration (SoftBank) — fundamentally different capital strategies.
- Geography stays U.S.-centric but diversifies. India (RISC-V/IP), Europe (AI accelerators / photonics), and Israel (AI chips) are visible as supply-chain diversification plays.
Global Semiconductor Market Snapshot
| Year | Market size | YoY | Key drivers |
|---|---|---|---|
| 2024 | $611.2B | — | Memory recovery, logic |
| 2025 | $791.7B | +29.4% | AI data centers, HBM |
| 2026 (est.) | $975.0B | +23.2% | Continued AI infrastructure |
300mm equipment spending (SEMI):
| Year | Equipment spend | Context |
|---|---|---|
| 2025 | ~$120B | AI ramp |
| 2026 | $133B | AI demand + supply-chain reshaping |
| 2027 | $151B | Continued investment cycle |
Concentration is in Memory/Logic. Peripheral layers — EDA, test, packaging — benefit indirectly as bottlenecks rather than as direct growth plays.
From doing DFM rollout on the floor: the more capital flows into equipment, the more profit quality is decided by the invisible yield-improvement margin around process data. That's a universal pattern, and EDA / inspection / DFM-adjacent plays remain investable, in my view, through this cycle.
The AI Infrastructure Bottleneck Map
Growing AI Infrastructure Demand
│
▼ Bottlenecks Redefined
┌───────────────┬───────────────────────────┬────────────────────────┬──────────────────────┐
│ Design Prod. │ Data Movement │ Packaging │ New Computing │
│ EDA/Verif. │ SerDes/Optics │ CPO/Chiplet │ Analog/Quantum │
└───────┬───────┴────────────┬──────────────┴─────────────┬──────────┴───────────┬──────────┘
↓ ↓ ↓ ↓
Seed→A: high Series B→E Late Long
software ratio Customer/Manufacturing Connection capital intensive tech/standard risk
Tier-1 VCs spread risk across these four constraint layers and capture upside where bottlenecks repeatedly resurface.
VC Strategy Comparison
| VC | Focus areas | Stage preference | Geography | Partnership / LP structure |
|---|---|---|---|---|
| Sequoia | Design AI (EDA/verification), RISC-V/IP, CPO | Seed → Growth | US, India | Public commitment to design AI; related vehicle in CPO |
| a16z | New compute (analog/mixed-signal), AI networking | Mega-seed + large Series B | US | Strategic Partnerships program for institutional GTM |
| Kleiner Perkins | RISC-V/IP, coherent DSP | Early → Series D | US | TSMC-backed fund reports → tightening supply-side ties |
| Bessemer | SerDes/IP, quantum, EDA automation | Series C core + early | US, Europe, Israel | Deep-tech commercialization across AI chips/quantum/EDA |
| SoftBank | AI chips/CPU/DPU, vertical integration | Growth → M&A | US, UK | Strategic LPs (Apple, etc.); Arm-centered AI Computing Segment |
Individual VC Profiles
Sequoia — Linking Design to Operations
Sequoia's thesis: as AI scales, chip design throughput becomes the bottleneck.
Selected deals:
- Ricursive Intelligence ($35M, 2025 Seed, lead) — AI-accelerated chip design.
- InCore Semiconductors ($3M, 2023 Seed) — India RISC-V IP.
- Mindgrove Technologies (~$2.3M, 2023 Seed) — India SoC.
- Ayar Labs ($500M, 2026 Series E, related vehicle) — Co-Packaged Optics. Co-investors include NVIDIA and AMD; valuation $3.75B.
Read: seed-stage focus on design productivity, late-stage extension into data movement (optical I/O) — wiring the design-to-operations bottleneck chain together.
a16z — Mega-Seeds on Compute Paradigms
a16z's signature move is massive seed checks on companies that could redefine entire compute categories.
- Unconventional AI ($475M, 2025 Seed, co-lead) — analog/mixed-signal optimized for probabilistic compute.
- Nexthop AI ($500M, 2026 Series B) — AI-cluster Ethernet switches; explicit thesis that the network is the new cluster bottleneck.
Read: where others spread early bets, a16z concentrates capital into paradigm-level bets at seed. The institutionalized Strategic Partnerships program (engineered GTM into government and enterprise) is a structural advantage that's hard to replicate.
Kleiner Perkins — Horizontal IP × Datacenter Optics
Kleiner gravitates to horizontal infrastructure: IP (RISC-V) and datacenter optics/interconnect.
- Akeana (>$100M cumulative, 2024 stealth launch) — RISC-V CPU/IP portfolio.
- Retym ($75M, 2025 Series D) — cloud/AI-optimized coherent DSP.
Read: target companies that win through design differentiation (IP/DSP) where the customer base is hyperscalers. The reported TSMC-backed fund signals deepening supply-side integration.
Bessemer — Commercializing Deep Tech
Bessemer treats SerDes/IP, quantum, and EDA automation as a single portfolio unified by deep technical moats with credible commercialization paths.
- ChipAgents ($21M, 2025 Series A, lead) — agentic AI for chip design and verification.
- Kandou ($92.3M, 2020 Series C, lead) — SerDes/IP, retimers.
- Rigetti ($79M, 2020 Series C, lead) — quantum hardware + cloud.
- Habana Labs ($75M Series B participant, 2018; Intel ~$2B acquisition, 2019) — AI chips.
Read: deep European/Israeli networks let Bessemer source technically differentiated companies early. Pattern is consistent — deep tech, plausible deployment path.
SoftBank — Vertical Integration as Strategy
Categorically different from the others. Not just investing in chip startups but assembling an integrated AI computing segment via M&A.
- Fungible ($200M, 2019 Series C, SVF lead) — DPU; later acquired by Microsoft.
- Graphcore (M&A, 2024, undisclosed) — UK AI chip.
- Ampere Computing ($6.5B announced 2025) — Arm-based cloud server CPU.
Arm + Ampere + Graphcore now sit inside one publicly disclosed AI Computing Segment. Strategic LPs in Fund I (PIF, Mubadala, Apple, Foxconn, Qualcomm, Sharp) embed semiconductor strategy at the fund-capital level.
Read: this is closer to strategic finance + operating company than traditional VC. Risk and time horizon are categorically different.
Investment Timeline
| Year | VC | Portfolio | Round | Amount ($M) | Domain |
|---|---|---|---|---|---|
| 2018 | Bessemer | Habana Labs | Series B (participant) | 75 | AI accelerator |
| 2019 | SoftBank | Fungible | Series C | 200 | DPU |
| 2020 | Bessemer | Kandou | Series C | 92.3 | SerDes/IP |
| 2020 | Bessemer | Rigetti | Series C | 79 | Quantum |
| 2023 | Sequoia | InCore Semiconductors | Seed | 3 | RISC-V IP |
| 2023 | Sequoia | Mindgrove | Seed | 2.3 | SoC |
| 2024 | Sequoia | Quantum Circuits | Series B | >60 | Quantum |
| 2024 | Kleiner Perkins | Akeana | Cumulative | >100 | RISC-V IP |
| 2024 | SoftBank Group | Graphcore | M&A | undisclosed | AI chip |
| 2025 | Sequoia | Ricursive Intelligence | Seed | 35 | Design AI/EDA |
| 2025 | a16z | Unconventional AI | Seed | 475 | Analog new compute |
| 2025 | Bessemer | ChipAgents | Series A | 21 | EDA automation |
| 2025 | Kleiner Perkins | Retym | Series D | 75 | Coherent DSP |
| 2025 | SoftBank Group | Ampere Computing | M&A | 6,500 | Arm CPU |
| 2026 | Sequoia (related) | Ayar Labs | Series E | 500 | CPO/Optical I/O |
| 2026 | a16z | Nexthop AI | Series B | 500 | AI switch |
Scenario Analysis & Investor Implications
Allocation by scenario
| Scenario | Probability | AI demand path | Active bottleneck | Suggested allocation |
|---|---|---|---|---|
| Base — continued expansion | 50% | +25%/yr | Design + data movement alternate | EDA/design AI + optical interconnect = core |
| Main — acceleration | 30% | +35%/yr | Packaging + power emerge as new limits | Add CPO/Chiplet/power-semis |
| Tail — slowdown | 20% | +10%/yr | Capacity overhang, pricing pressure | Trim equipment/material cyclicals; rotate to IP/EDA |
Practical angles for Japan-based investors
From watching the Japanese semiconductor ecosystem from inside CVC, the realistic angles are: (1) manufacturing equipment, materials, and test — incumbents with global moats; (2) design IP and EDA automation — software-leaning, lower entry barriers. The thing I felt most strongly from the floor is that process/equipment data ecosystems are very hard to build from outside, and this is where Japan retains structural advantage.
ZYL0's Take
In one line: semiconductor investing means buying AI's constraints, not its compute.
If GPU performance keeps scaling, design, interconnect, packaging, and supply chain rotate through the role of "current bottleneck." That mirrors a pattern I learned from process work: the more capital pours into equipment, the more profit quality gets decided by yield and process data downstream. The VC bets reflect that.
Part 2 goes deeper on each technology domain — investment logic, case studies, and what separates winners from losers per vertical.
Next Issue Ideas
- Idea 1: A data-updated follow-up — Revisit the thesis with fresh numbers and separate what strengthened from what broke.
- Idea 2: A practical template edition — Turn the article into a checklist readers can reuse for investing, pricing, or technical operations.
- Idea 3: The bear-case test — Define the conditions that would invalidate this view and map the indicators to watch next.
Related Posts
- Why Design, Data Movement & Packaging Attract VC Capital — Series② — As GPU performance scales, design, I/O, and packaging become the real AI bottleneck.
- Semiconductor VC Series③: Designing for Volatility — Why Tier-1 VCs decompose semiconductor investing into "design productivity, data movement, packaging, supply chain" ra…
- Reading the 9 NPU / AI-Accelerator Developers From the Outside: An Edge-Inference Investment Map and Its Public Proxies — An outside-in read of nine NPU developers — the NVIDIA-Groq consolidation, memory-wall architecture splits, public proxies,…
References
The factual and numerical assumptions in this article are anchored to primary or public materials that readers can revisit during AdSense review and future updates.
This article is for informational purposes only and does not constitute investment advice or a recommendation of any specific stock, service, or contract structure. The author may hold positions or interests related to companies or services mentioned. Generative AI was used for parts of research, translation, and proofreading, with final review by ZYL0. See the disclaimer for details.

































































